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50 a, 2 mm 1.7 mm wlcsp, low noise, heart rate monitor for wearable products data sheet AD8233 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features fully integrated, single-lead electrocardiogram (ecg) front end low quiescent supply current: 50 a (typical) leads on/off detection while in shutdown (<1 a) common-mode rejection ratio: 80 db (dc to 60 hz) 2 or 3 electrode configurations high signal gain (g = 100) with dc blocking capabilities 2-pole adjustable high-pass filter accepts up to 300 mv of half cell potential fast restore feature improves filter settling uncommitted op amp 3-pole adjustable low-pass filter with adjustable gain integrated right leg drive (rld) amplifier with shutdown single-supply operation: 1.7 v to 3.5 v integrated reference buffer generates virtual ground rail-to-rail output internal rfi filter 8 kv human body model (hbm) esd rating shutdown pin 2 mm 1.7 mm wlcsp applications fitness and activity heart rate monitors portable ecg wearable and remote health monitors gaming peripherals biopotential signal acquisition, such as emg functional block diagram lod AD8233 +v s gnd opamp? out refout opamp+ sw refin iaout hpsense hpdrive +in ?in rld rldfb fr sdn ac/dc leads off detection 10k ? 10k ? 150k ? s1 s2 a4 b5 a5 c5 c4 b4 a3 a2 a1 b3 ia a3 d5 d4 d3 c3 d2 d1 a1 a2 b2 b1 c2 c1 c rld sdn 13737-001 figure 1. general description the AD8233 is an integrated signal conditioning block for ecg and other biopotential measurement applications. it is designed to extract, amplify, and filter small biopotential signals in the presence of noisy conditions, such as those created by motion or remote electrode placement. this design allows an ultralow power analog-to-digital converter (adc) or an embedded microcontroller to easily acquire the output signal. the AD8233 implements a two-pole high-pass filter for eliminating motion artifacts and the electrode half cell potential. this filter is tightly coupled with the instrumentation architec- ture of the amplifier to allow both large gain and high-pass filtering in a single stage, thereby saving space and cost. an uncommitted operational amplifier enables the AD8233 to create a three-pole, low-pass filter to remove additional noise. the user can select the frequency cutoff of all filters to suit different types of applications. to improve the common-mode rejection of the line frequencies in the system and other undesired interferences, the AD8233 includes an amplifier for driven lead applications, rld. the AD8233 includes a fast restore function that reduces the duration of the otherwise long settling tails of the high-pass filters. after an abrupt signal change that rails the amplifier (such as a leads off condition), the AD8233 automatically adjusts to a higher filter cutoff. this feature allows the AD8233 to recover quickly, and therefore, to take valid measurements soon after connecting the electrodes to the subject. the AD8233 is available in a 2 mm 1.7 mm, 20-ball wlcsp package. performance is specified from 0c to 70c and is operational from ?40c to +85c. table 1. ad8232 vs. AD8233 comparison parameter ad8232 AD8233 supply current 170 a 50 a peak-to-peak voltage noise (f = 0.5 hz to 40 hz) 14 v p-p 8.5 v leads on/off detection in shutdown not included included right leg drive shutdown not included included package size 4 mm 4 mm 0.75 mm 2 mm 1.7 mm 0.5 mm
AD8233* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? AD8233 evaluation board documentation data sheet ? AD8233: 50 a, 2 mm 1.7 mm wlcsp, low noise, heart rate monitor for wearable products data sheet user guides ? ug-1016: evaluating the AD8233 50 a, 2 mm 1.7 mm wlcsp, low noise, heart rate monitor for wearable products tools and simulations ? ad8232/AD8233 filter design tool ? AD8233 spice macro-model design resources ? AD8233 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD8233 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
AD8233 data sheet rev. 0 | page 2 of 29 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? instrumentation amplifier performance characteristics ....... 8 ? operational amplifier performance characteristics ............. 11 ? right leg drive (rld) amplifier performance characteristics ............................................................................ 14 ? reference buffer performance characteristics ....................... 15 ? system performance characteristics ....................................... 16 ? theory of operation ...................................................................... 17 ? architecture overview .............................................................. 17 ? instrumentation amplifier ........................................................ 17 ? operational amplifier ............................................................... 17 ? right leg drive amplifier ......................................................... 18 ? reference buffer ......................................................................... 18 ? fast restore circuit .................................................................... 18 ? leads on/off detection ............................................................ 19 ? standby operation ..................................................................... 20 ? input protection ......................................................................... 21 ? radio frequency interference (rfi) ........................................ 21 ? power supply regulation and bypassing ................................ 21 ? input referred offsets ............................................................... 21 ? layout recommendations ........................................................ 21 ? applications information .............................................................. 22 ? eliminating electrode offsets................................................... 22 ? high-pass filtering ..................................................................... 22 ? low-pass filtering and gain ..................................................... 24 ? driven electrode ........................................................................ 25 ? application circuits ....................................................................... 26 ? heart rate measurement (hrm) next to the heart ............. 26 ? exercise applicationheart rate measured at the hands .. 26 ? holter monitor configuration ................................................. 27 ? synchronized ecg and ppg measurement ........................... 28 ? packaging and ordering information ......................................... 29 ? outline dimensions ................................................................... 29 ? ordering guide .......................................................................... 29 ? revision history 8/2016revision 0: initial version
data sheet AD8233 rev. 0 | page 3 of 29 specifications +v s = 1.8 v to 3 v 5.5%, v ref = +v s /2, v cm = +v s /2, t a = 25c, fr = low, sdn = high, ac/ dc = low, rld sdn = low, unless otherwise noted. table 2. parameter symbol test conditions/comments min typ max unit instrumentation amplifier common-mode rejection ratio, dc to 60 hz cmrr v cm = 0.35 v to +v s ? 150 mv, v diff = 0 v 80 86 db v cm = 0.35 v to +v s ? 150 mv, v diff = 0.3 v 80 db power supply rejection ratio psrr +v s = 1.8 v to 3.5 v 76 90 db offset voltage (rti) v os instrumentation amplifier inputs 1 6 mv dc blocking input 1 25 v average offset drift instrumentation amplifier inputs 2 v/c dc blocking input 1 0.05 v/c input bias current i b 50 200 pa t a = 0c to 70c 1 na input offset current i os 25 100 pa t a = 0c to 70c 1 na input impedance differential 10||7.5 g||pf common mode 5||15 g||pf input voltage noise (rti) spectral noise density f = 1 khz 150 nv/hz peak-to-peak voltage noise f = 0.1 hz to 10 hz 10 v p-p f = 0.5 hz to 40 hz 8.5 v p-p input voltage range t a = 0c to 70c 0.2 +v s v dc differential input range v diff ?300 +300 mv output output swing r l = 50 k 0.1 +v s ? 0.1 v short-circuit current i out 6.3 ma gain a v 100 v/v gain error v diff = 0 v 0.4 % v diff = ?300 mv to +300 mv 1 4 % average gain drift t a = 0c to 70c 12 ppm/c bandwidth bw 1 khz rfi filter cutoff (each input) 1 mhz operational amplifier (a1) offset voltage v os 1 5 mv average temperature coefficient tc t a = 0c to 70c 1 v/c input bias current i b 100 pa t a = 0c to 70c 1 na input offset current i os 100 pa t a = 0c to 70c 1 na input voltage range 0.1 +v s ? 0.1 v common-mode rejection ratio cmrr v cm = 0.5 v to +v s ? 0.5 v 100 db power supply rejection ratio psrr 100 db large signal voltage gain a vo 110 db output voltage range r l = 50 k 0.1 +v s ? 0.1 v short-circuit current limit i out 12 ma gain bandwidth product gbp 15 khz
AD8233 data sheet rev. 0 | page 4 of 29 parameter symbol test conditions/comments min typ max unit slew rate sr 0.01 v/s voltage noise density (rti) e n f = 1 khz 120 nv/hz peak-to-peak voltage noise (rti) e n p-p f = 0.1 hz to 10 hz 7 v p-p f = 0.5 hz to 40 hz 9 v p-p right leg drive amplifier (a2) quiescent supply current 7.5 10 a output swing r l = 50 k 0.1 +v s ? 0.1 v short-circuit current i out 11 ma integrator input resistor 120 150 180 k gain bandwidth product gdp 20 khz reference buffer (a3) offset error v os r l > 50 k 1 mv input bias current i b 100 pa short-circuit current limit i out 12 ma voltage range r l = 50 k 0.1 +v s ? 0.7 v dc leads off comparators threshold voltage +v s ? 0.27 v hysteresis 125 mv propagation delay 1.5 s ac leads off detector square wave frequency f ac 50 100 175 khz square wave amplitude i ac 200 na p-p input currents in shutdown mode 2 i dc +in, sdn = low 250 na ?in, sdn = low ?300 na impedance threshold between +in and ?in, sdn = high 10 20 m detection delay 100 s fast restore circuit switches s1 and s2 on resistance r on 8 10 12 k off leakage 100 pa window comparator threshold voltage from either rail 100 mv propagation delay 2 s switch timing characteristics feedback recovery switch on time t s1 +v s = 3 v 160 ms +v s = 1.8 v 80 filter recovery switch on time t s2 +v s = 3 v 80 ms +v s = 1.8 v 40 fast restore reset t rst +v s = 3 v 3 s +v s = 1.8 v 1.5 logic interface input characteristics input voltage (ac/dc , fr, and rld sdn ) low v il 0.41 +v s v high v ih 0.45 +v s v input voltage (sdn ) low v il 0.6 +v s v high v ih 0.3 +v s v output characteristics lod terminal output voltage r l = 100 k low v ol 0.05 v high v oh +v s ? 0.05 v
data sheet AD8233 rev. 0 | page 5 of 29 parameter symbol test conditions/comments min typ max unit system specifications quiescent supply current 50 70 a t a = 0c to 70c 60 a wakeup current sdn = low, lod = low 0.65 1.5 a t a = 0c to 70c 0.75 a shutdown current sdn = low, lod = high 0.5 1 a t a = 0c to 70c 0.6 a peak-to-peak voltage noise (rti) v diff = 0 v f = 0.5 hz to 40 hz 9 v p-p f = 0.05 hz to 150 hz 15 v p-p v diff = 0.3 v f = 0.5 hz to 40 hz 11 v p-p f = 0.05 hz to 150 hz 21 v p-p supply range 1.7 3.5 v specified temperature range 0 70 c operational temperature range ?40 +85 c 1 offset referred to the input of the instrumentation amplifier inputs. 2 in ac leads off and shutdown mode, the dc leads off comparator at the +in pin trips the lod pin.
AD8233 data sheet rev. 0 | page 6 of 29 absolute maximum ratings table 3. parameter rating supply voltage 3.6 v output short-circuit current duration indefinite maximum voltage, any terminal 1 +v s + 0.3 v minimum voltage, any terminal 1 ?0.3 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c maximum junction temperature 140c esd rating hbm 8 kv charged device model (ficdm) 1 kv 1 this level or the maximum specified su pply voltage, whiche ver is the lesser, indicates the superior voltage limit for any terminal. if input voltages beyond the specified minimum or maximum voltages are expected, place resistors in series with the inputs to limit the current to less than 5 ma. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. table 4. thermal resistance package type pcb power (w) ja (c/w) jc (c/w) 0 ms 1 ms 2 ms cp-20-13 1s0p 1 0.25 108.5 89.0 82.3 0.6 1.25 101.1 87.3 87.3 0.6 2s2p 2 0.25 47.9 43.4 42.1 0.7 1.25 46.8 43.3 42.1 0.7 1 simulated thermal numbers per jesd51-9: 1-layer pcb (1s0p), low effective thermal conductivity test board. 2 4-layer pcb (2s2p), high effective thermal conductivity test board. esd caution
data sheet AD8233 rev. 0 | page 7 of 29 pin configuration and fu nction descriptions top view (ball side down) not to scale a d8233 1 a b c d 234 ball a1 indicator 5 gnd +v s refin hpsense hpdrive sdn ac/dc fr iaout +in lod rld sdn refout rldfb ?in out opamp? opamp+ sw rld 13737-002 figure 2. pin configuration table 5. pin function descriptions pin no. mnemonic description a1 gnd power supply ground. a2 +v s power supply terminal. a3 refin reference buffer input. use refin, a high impedance input terminal, to set the level of the reference buffer. a4 hpsense high-pass sense input for instrumentation amplifier. conn ect hpsense to the junction of r and c that sets the corner frequency of the dc blocking circuit. a5 hpdrive high-pass driver output. connect hpdrive to th e capacitor in the first high-pass filter. the AD8233 drives this pin to keep hpsense at the same level as the reference voltage. b1 sdn shutdown control input. drive sdn low to enter the low power shutdown mode. b2 ac/dc leads off mode control input. drive the ac/dc pin low for dc leads off mode. drive the ac/dc pin high for ac leads off mode. b3 fr fast restore control input. drive fr high to enable fast recovery mode; otherwise, drive it low. b4 iaout instrumentation amplifier output terminal. b5 +in instrumentation amplifier, positive input. +in is typically connected to the left arm (la) electrode. c1 lod leads off detection (lod) comparator output. c2 rld sdn right leg drive shutdown control input. drive rld sdn low to power down the rld amplifier. c3 refout reference buffer output. the instrumentation amplifier o utput is referenced to this potential. use refout as a virtual ground for any point in the circuit that requires a signal reference. c4 rldfb right leg drive feedback input. rldfb is th e feedback terminal for the right leg drive circuit. c5 ?in instrumentation amplifier, negative input. ?in is typically connected to the right arm (ra) electrode. d1 out operational amplifier output. the fully conditioned heart rate signal is present at this output. out can be connected to the input of an adc. d2 opamp? operational amplifier inverting input. d3 opamp+ operational amplifier noninverting input. d4 sw fast restore switch terminal. connect this te rminal to the output of the second high-pass filter. d5 rld right leg drive output. connect the driven electrode (typically, right leg) to the rld pin.
AD8233 data sheet rev. 0 | page 8 of 29 typical performance characteristics +v s = 3 v, v ref = 1.5 v, v cm = 1.5 v, t a = 25c, unless otherwise noted. instrumentation amplifier performance characteristics 2100 1750 350 700 1050 1400 0 ?120 ?90 90 6030 0 ?60 ?30 120 units cmrr (v/v) 13737-003 figure 3. cmrr distribution 3500 3000 500 1000 1500 2500 0 ?2.0 ?1.5 1.5 1.0 0.5 0 ?1.0 ?0.5 2.0 units gain error (%) 13737-004 figure 4. gain error distribution 3.5 3.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 3.5 3.0 2.5 2.0 1.5 input common-mode voltage (v) output voltage (v) 13737-005 figure 5. input common-mode voltage vs. output voltage 100 ?100 0 0.5 1.0 3.5 3.0 2.5 2.0 1.5 input bias current (pa) input common-mode voltage (v) ?80 ?60 ?40 ?20 0 20 40 60 80 13737-006 figure 6. input bias current vs. input common-mode voltage 50 40 30 20 10 0 ?10 1 100k 10k 1k 100 10 gain (db) frequency (hz) no dc offset 300mv offset 13737-007 figure 7. gain vs. frequency 120 100 40 60 80 20 10 100k 10k 1k 100 cmrr (db) frequency (hz) no dc offset +300mv offset ?300mv offset 13737-008 figure 8. cmrr vs. frequency (rti)
data sheet AD8233 rev. 0 | page 9 of 29 100 0 0.1 1 10 100k 10k 1k 100 psrr (db) frequency (hz) 10 20 30 40 50 60 70 80 90 13737-009 figure 9. psrr vs. frequency (rti) 10k 1k 100 10 0.1 1 10 100k 10k 1k 100 noise (nv/ hz) frequency (hz) 13737-010 figure 10. voltage noise spectral density (rti) 5v/div 1s/div 13737-011 figure 11. 0.1 hz to 10 hz noise (rti) 5v/div 200ms/div 13737-012 figure 12. 0.5 hz to 40 hz noise (rti) 1.0 0 050 300 250 200 150 100 gain error (%) dc offset (mv) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 13737-013 figure 13. gain error vs. dc offset 50mv/div 400s/div 22pf 470pf 1nf 13737-014 figure 14. small signal pulse response
AD8233 data sheet rev. 0 | page 10 of 29 400s/div 0.5v/div 13737-015 figure 15. large signal pulse response 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 100 1m 100k 10k 1k output voltage swing (v) load ( ? ) ?40c +25c +85c 13737-016 figure 16. output voltage swing vs. load 0.4 ?0.4 ?40 ?20 0 20 40 60 100 80 dc blocking input offset (mv) temperature (c) ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 13737-017 figure 17. dc blocking input offset drift 4.0 ?1.0 ?40 ?20 0 20 40 60 80 100 input bias current (na) input offset current (pa) temperature (c) ?20 ?10 0 10 20 30 40 50 60 70 80 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i b i os 13737-018 figure 18. input bias current (i b ) and input offset current (i os ) vs. temperature 0.5 ?0.5 ?40 ?20 0 100 80 60 40 20 gain error (%) temperature (c) ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 13737-019 figure 19. gain error vs. temperature 10 ?10 ?40 ?20 0 100 80 60 40 20 cmrr (v/v) temperature (c) ?8 ?6 ?4 ?2 0 2 4 6 8 13737-020 figure 20. cmrr vs. temperature
data sheet AD8233 rev. 0 | page 11 of 29 operational amplifier performance characteristics 1000 200 400 600 800 0 ?4 ?2 0 4 2 units offset voltage (mv) 13737-021 figure 21. offset distribution 120 ?60 0.1 1 10 100k 10k 1k 100 open-loop gain (db) frequency (hz) ?40 ?20 0 20 40 60 80 100 0 ?180 phase margin (degrees) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 gain phase margin 13737-022 figure 22. open-loop gain and phase margin vs. frequency 20mv/div 100s/div 22pf 470pf 1nf 13737-023 figure 23. small signal response for various capacitive loads 400s/div 0.5v/div 13737-024 figure 24. large signal transient response 10k 1k 100 10 0.1 1 10 100k 10k 1k 100 voltage noise spectral density (nv/ hz) frequency (hz) 13737-025 figure 25. voltage noise spectral density vs. frequency 5v/div 1s/div 13737-026 figure 26. 0.1 hz to 10 hz noise
AD8233 data sheet rev. 0 | page 12 of 29 5v/div 200ms/div 13737-027 figure 27. 0.5 hz to 40 hz noise 100 ?100 03.5 input bias current (pa) input common-mode voltage (v) ?80 ?60 ?40 ?20 0 20 40 60 80 0.5 1.0 1.5 2.0 2.5 3.0 13737-028 figure 28. input bias current vs. input common-mode voltage 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 100 1m 100k 10k 1k output voltage swing (v) load ( ? ) ?40c +25c +85c 13737-029 figure 29. output voltage swing vs. load 120 0 10 20 0.1 1 10 100k 10k 1k 100 psrr (db) frequency (hz) 30 40 50 60 70 80 90 100 110 13737-030 figure 30. power su pply rejection ratio
data sheet AD8233 rev. 0 | page 13 of 29 50mv/div 100s/div 13737-031 figure 31. load transient response (100 a load change) 0.8 ?0.8 ?40 ?20 0 20 40 60 100 80 offset (mv) temperature (c) ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 13737-032 figure 32. offset vs. temperature 1k 100 10 1 0.1 ?40 100 input bias current (pa) temperature (c) ?20 0 20 40 60 80 13737-033 figure 33. input bias current vs. temperature
AD8233 data sheet rev. 0 | page 14 of 29 right leg drive (rld) amplifier performance characteristics 140 ?40 0.1 1 10 100k 10k 1k 100 open-loop gain (db) frequency (hz) ?20 0 20 40 60 80 100 120 0 ?180 phase margin (degrees) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 gain phase margin 13737-034 figure 34. open-loop gain and phase margin vs. frequency 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 100 1m 100k 10k 1k output voltage swing (v) load ( ? ) ?40c +25c +85c 13737-035 figure 35. output voltage swing vs. load 10k 1k 100 10 0.1 1 10 100k 10k 1k 100 voltage noise spectral density (nv/ hz) frequency (hz) 13737-036 figure 36. voltage spectral noise density vs. frequency 5v/div 1s/div 13737-037 figure 37. 0.1 hz to 10 hz noise 5v/div 200ms/div 13737-038 figure 38. 0.5 hz to 40 hz noise 12 0 ?40 100 rld supply current (a) temperature (c) ?20 20 0 406080 2 4 6 8 10 +v s = 1.8v +v s = 3v +v s = 3.5v ac/dc = low, rld sdn = high 13737-039 figure 39. rld supply current vs. temperature
data sheet AD8233 rev. 0 | page 15 of 29 reference buffer performance characteristics 15 ?15 0.01 10 1 0.1 output error (mv) load current (ma) ?10 ?5 0 5 10 source sink 13737-040 figure 40. load regulation 50mv/div 100s/div 13737-041 figure 41. load transient response (100 a load change) 100k 10k 10 100 1k 1 0.1 1 10 100k 10k 1k 100 output impedance ( ? ) frequency (hz) 13737-042 figure 42. output im pedance vs. frequency 1k 100 10 1 0.1 ?40 100 input bias current (pa) temperature (c) ?20 0 20406080 13737-043 figure 43. input bias current vs. temperature
AD8233 data sheet rev. 0 | page 16 of 29 system performance characteristics 80 0 ?40 100 supply current (a) temperature (c) ?20 20 0406080 10 20 30 40 50 60 70 +v s = 1.8v +v s = 3v +v s = 3.5v sdn = high, ac/dc = low, rld sdn = low 13737-044 figure 44. supply current vs. temperature 900 0 ?40 100 shutdown current (na) temperature (c) ?20 20 0406080 100 200 300 400 500 600 700 800 sdn = low, ac/dc = low rld sdn = low, lod = high +v s = 1.8v +v s = 3v +v s = 3.5v 13737-045 figure 45. shutdown current vs. temperature 900 0 ?40 100 wakeup current (na) temperature (c) ?20 20 0406080 100 200 300 400 500 600 700 800 sdn = low, ac/dc = low rld sdn = low, lod = low +v s = 1.8v +v s = 3v +v s = 3.5v 1000 13737-046 figure 46. wakeup current vs. temperature 10k 1k 100 10 0.1 1 10 100k 10k 1k 100 voltage noise spectral density (nv/ hz) frequency (hz) 13737-047 figure 47. voltage noise spectral density (rti) (measured at iaout) 5v/div 200ms/div 13737-048 figure 48. 0.5 hz to 40 hz noise (rti) (measured at iaout) 10v/div 2s/div 13737-049 figure 49. 0.05 hz to 150 hz noise (rti) (measured at iaout)
data sheet AD8233 rev. 0 | page 17 of 29 theory of operation 10k ? iaout hpsense hpdrive s1 gm1 gm2 99r r + v s 0.7v instrumentation amplifier (ia) +v s ? 0.1v 0.1v refout refin ?in +in fr v cm c1 rld sdn lod +v s ? 0.27v sw opamp+ opamp? out rld rldfb gnd 150k ? 10k ? hpa +v s = refout charge pump sync rectifier switch timing a3 a2 a1 ac/dc ac/dc ac/dc ac/dc sdn s1 s2 s2 b4 c5 b5 c4 d5 a3 d4 d3 d2 d1 a5 a4 b3 b2 b1 c1 c2 a2 a1 c3 *all switches shown in dc leads off detection position and fast restore disabled rfi filter 13737-050 figure 50. simplified schematic diagram architecture overview the AD8233 is an integrated front end for signal conditioning of cardiac biopotentials for heart rate monitoring. it consists of a specialized instrumentation amplifier (ia), an operational amplifier (a1), a right leg drive amplifier (a2), and a midsupply reference buffer (a3). in addition, the AD8233 includes leads on/off detection circuitry and an automatic fast restore circuit that restores the signal shortly after leads are reconnected. the AD8233 contains a specialized instrumentation amplifier that amplifies the ecg signal while rejecting the electrode half cell potential on the same stage. the amplification of the ecg signal and the rejection of the electrode half cell potential are possible with an indirect current feedback architecture, which reduces size and power compared with traditional implementations. instrumentation amplifier the instrumentation amplifier is shown in figure 50 as comprised by two well matched transconductance amplifiers (gm1 and gm2), the dc blocking amplifier (hpa), and an integrator formed by c1 and an op amp. the transconductance amplifier, gm1, generates a current that is proportional to the voltage present at its inputs. when the feedback is satisfied, an equal voltage appears across the inputs of the transconductance amplifier, gm2, thereby matching the current generated by gm1. the difference generates an error current that is integrated across capacitor c1. the resulting voltage appears at the output of the instrumentation amplifier. the feedback of the amplifier is applied via gm2 through two separate paths: the two resistors divide the output signal to set an overall gain of 100, whereas the dc blocking amplifier integrates any deviation from the reference level. consequently, dc offsets as large as 300 mv across the gm1 inputs appear inverted and with the same magnitude across the inputs of gm2, all without saturating the signal of interest. to increase the common-mode voltage range of the instrumen- tation amplifier, a charge pump boosts the supply voltage for the two transconductance amplifiers. this boost in supply voltage further prevents saturation of the amplifier in the presence of large common-mode signals, such as line interference. the charge pump runs from an internal oscillator, the frequency of which is set around 500 khz. operational amplifier the general-purpose operational amplifier (a1) is a rail-to-rail device that can be used for low-pass filtering and to add additional gain. the following sections provide details and example circuits that use this amplifier.
AD8233 data sheet rev. 0 | page 18 of 29 right leg drive amplifier the right leg drive (rld) amplifier inverts the common-mode signal that is present at the instrumentation amplifier inputs. when the right leg drive output current is injected into the subject, it counteracts common-mode voltage variations, thus improving the common-mode rejection of the system. the common-mode signal that is present across the inputs of the instrumentation amplifier is derived from the transconduct- ance amplifier, gm1. it is then connected to the inverting input of a2 through a 150 k resistor. an integrator can be built by connecting a capacitor between the rld fb and rld terminals. a good starting point is a 1 nf capacitor, which places the crossover frequency at about 1 khz (the frequency at which the amplifier has an inverting unity gain). this configuration results in about 26 db of loop gain available at a frequency range from 50 hz to 60 hz for common-mode line rejection. higher capacitor values reduce the crossover frequency, thereby reducing the gain that is available for rejection and, consequently, increasing the line noise. lower capacitor values move the crossover frequency to higher frequencies, allowing increased gain. the tradeoff is that with higher gain, the system can become unstable and saturate the output of the right leg amplifier. when using this amplifier to drive an electrode, place a resistor in series with the output to limit the current to be always less than 10 a, even in fault conditions. for example, if the supply used is 3.0 v, ensure that the resistor is greater than 330 k to account for component and supply variations. rld 1nf r* *limit current to less than 10a. rldfb a2 refout to driven electrode 150k ? v cm 18 d5 c4 13737-051 figure 51. typical configuration of right-leg drive circuit in two electrode configurations, a2 can be shut down by setting rld sdn low for additional power savings. if left in shutdown, it is recommended to leave both rld and rldfb floating. alternatively, rld can be used to bias the inputs through 10 m resistors as described in the leads on/off detection section. when the AD8233 is in shutdown and dc leads off detection mode, rld pulls down towards ground. this pull- down acts as an lod wake-up function, pulling the inputs down when the electrodes are reconnected. reference buffer the AD8233 operates from a single supply. to simplify the design of single-supply applications, the AD8233 includes a reference buffer to create a virtual ground between the supply voltage and the system ground. the signals present at the out- put of the instrumentation amplifier are referenced around this voltage. for example, if there is zero differential input voltage, the voltage at the output of the instrumentation amplifier is this reference voltage. the reference voltage level is set at the refin pin. it can be set with a voltage divider or by driving the refin pin from some other point in the circuit (for example, from the adc reference). the voltage is available at the refout pin for the filtering circuits or for an adc input. refin a3 a3 r1 r2 c1 +v s 13737-052 figure 52. setting the internal reference to limit the power consumption of the voltage divider, the use of large resistors is recommended, such as 10 m. the designer must keep in mind that high resistor values make it easier for interfering signals to appear at the input of the reference buffer. to minimize noise pickup, it is recommended to place the resistors close to each other and as near as possible to the refin terminal. furthermore, use a capacitor in parallel with the lower resistor on the divider for additional filtering, as shown in figure 52. keep in mind that a large capacitor results in better noise filtering but it takes longer to settle the reference after power-up. the total time it takes the reference to settle within 1% can be estimated with the formula t settle_reference = r2r1 c1r2r1 ? ? ? ? 5 note that disabling the AD8233 with the shutdown terminal does not discharge this capacitor. fast restore circuit because of the low cutoff frequency used in high-pass filters in ecg applications, signals may require several seconds to settle. this settling time can result in a frustrating delay for the user after a step response: for example, when the electrodes are first connected. this fast restore function is implemented internally, as shown in figure 53. the output of the instrumentation amplifier is connec- ted to a window comparator. the window comparator detects a saturation condition at the output of the instrumentation amplifier when its voltage approaches 0.1 v from either supply rail. switch timing s1 s2 lod fr b3 iaout 0.1v +in ?in ia b5 c5 +v s ? 0.1v c1 13737-053 figure 53. fast restore circuit
data sheet AD8233 rev. 0 | page 19 of 29 leads off leads on s1 s2 saturation detected no saturation t s1 t s2 t rst 13737-054 figure 54. timing diagram for fast restore switches (time base not to scale) if this saturation condition is present when both input electrodes are attached to the subject, the comparator triggers a timing circuit that automatically closes switch s1 and switch s2 (see figure 54 for a timing diagram). these two switches (s1 and s2) enable two different 10 k resistor paths: one between hpsense and iaout and another between sw and refout. during the time switch s1 and switch s2 are enabled, these internal resistors appear in parallel with their corresponding external resistors forming high-pass filters. the result is that the equivalent lower resistance shifts the pole to a higher frequency, delivering a quicker settling time. note that the fast restore settling time depends on how quickly the internal 10 k resistors of the AD8233 can drain the capacitors in the high-pass circuit. smaller capacitor values result in a shorter settling time. if, by the end of the timing, the saturation condition persists, the cycle repeats. otherwise, the AD8233 returns to its normal operation. if either of the leads off comparator outputs is indi- cating that an electrode is disconnected, the timing circuit is prevented from triggering because it is assumed that no valid signal is present. to disable fast restore, drive the fr pin low or tie it permanently to gnd. leads on/off detection the AD8233 includes leads off detection. it features ac and dc detection modes that both work with two and three electrode configurations. ultralow power comparators allow the leads on/off detection to remain functional in shutdown mode, allowing power savings at the system level when the lod output is used as a wake-up signal for the microcontroller. dc leads on/off detection the dc leads off detection mode can be used in two or three electrode configurations. it works by sensing when either instrumentation amplifier input voltage is within 0.27 v from the positive rail. the lowest power use case for the AD8233 is two electrode dc mode. a pull-up resistor on +in and a pull- down resistor on ?in creates a voltage divider when the electrodes are connected, setting the input common mode to midsupply. when the electrodes disconnect, the comparator monitoring +in sets lod high when the input pulls to +v s . 10m ? 10m ? ia b5 c5 + v s 13737-055 figure 55. circuit configuration for two electrode dc leads off detection for three electrode dc mode, each input must have a pull-up resistor connected to the positive supply. during normal operation, the potential of the subject must be inside the common-mode range of the instrumentation amplifier, which is only possible if a third electrode is connected to the output of the right leg drive amplifier. rld 10m ? ? to driven electrode ia b5 c5 d5 + v s 13737-056 figure 56. circuit configuration for three electrode dc leads off detection the AD8233 indicates when any electrode is disconnected by setting the lod pin high. to use this mode, connect the ac/ dc pin to ground.
AD8233 data sheet rev. 0 | page 20 of 29 ac leads on/off detection the ac leads off detection mode is useful when using two electrodes. in this case, a conduction path must exist between the two electrodes, which is usually formed by two resistors, as shown in figure 57. these resistors also provide a path for bias return on each input. connect each resistor to refout or rld to maintain the inputs within the common-mode range of the instrumentation amplifier. refout 10m ? ? ia b5 c5 a2 c3 +v s 13737-057 figure 57. circuit configuration for two electrode ac leads off detection the AD8233 detects when an electrode is disconnected by forcing a small 100 khz current into the input terminals. this current flows through the external resistors from in+ to in? and develops a differential voltage across the inputs, which is then synchronously detected and compared to an internal threshold. the recommended value for these external resistors is 10 m. low resistance values make the differential drop too low to be detected and lower the input impedance of the amplifier. when the electrodes are attached to the subject, the impedance of this path must be less than 3 m to maintain the drop below the threshold of the comparator. to use the ac leads off mode, tie the ac/ dc pin to the positive supply rail. note that, whereas refout is at a constant voltage value, using the rld output as the input bias may be more effective in rejecting common-mode interference at the expense of additional power. in three electrode ac leads off detection mode, as shown in figure 58, pull-up resistors are not required, which improves the input impedance of the circuit. this mode is beneficial for dry electrode applications. the ac mode currents contribute 1/f noise to the system; therefore, depending on the application, it may be advantageous to use ac leads off detection as a spot check and then switching to dc mode for improved ecg acquisition. rld ia b5 c5 a2 d5 +v s to driven electrode 13737-058 figure 58. circuit configuration for three electrode ac leads off detection the ac leads off detection mode continues to function in shutdown mode as well. to keep the power under 1 a, the clock is disabled and the ac currents become dc currents. the current source on +in is 250 na, while the current sink on Cin is ?300 na. the stronger pull-down current on ?in acts as a wake-up function, pulling lod low when the electrodes are reconnected. standby operation the AD8233 includes a shutdown pin ( sdn ) that further enhances the flexibility and ease of use in portable applications where power consumption is critical. a logic level signal can be applied to this pin to switch to shutdown mode, even when the supply is still on. driving the sdn pin low places the AD8233 in shutdown mode and draws less than 1 a of supply current, offering considerable power savings. to enter normal operation, drive sdn high; when not using this feature, permanently tie sdn to +v s . during shutdown operation, the AD8233 cannot maintain the refout voltage, but it does not drain the refin voltage, thereby maintaining this additional conduction path from the supply to ground. when emerging from a shutdown condition, the charge stored in the capacitors on the high-pass filters can saturate the instru- mentation amplifier and subsequent stages. the use of the fast restore feature helps reduce the recovery time and, therefore, minimize on time in power sensitive applications. using leads on/off detection in shutdown mode allows system level power saving. the microcontroller enters sleep mode when the electrodes are disconnected, and the lod signal acts as an interrupt to wake up the microcontroller. an example of this functionality is shown in figure 59. 1 - at least one electrode is off and therefore lod output is high. mcu is off and sdn is low. (AD8233 shutdown current < 1a) 2 - lod goes low when both electrodes are connected. a falling edge at lod wakes up the mcu. 3 - mcu wakes up and sets sdn high. 4 - AD8233 is active (~50a) and monitoring ecg. 250mv/div 400ms/div out sdn lod 13737-059 figure 59. electrode connection and system wakeup sequence
data sheet AD8233 rev. 0 | page 21 of 29 input protection all terminals of the AD8233 are protected against esd. in addition, the input structure allows dc overload conditions that are a diode drop above the positive supply and a diode drop below the negative supply. voltages beyond a diode drop of the supplies cause the esd diodes to conduct and enable current to flow through the diode. therefore, use an external resistor in series with each of the inputs to limit current for voltages beyond the supplies. in either scenario, the AD8233 safely handles a continuous 5 ma current at room temperature. for applications where the AD8233 encounters extreme over- load voltages, such as in cardiac defibrillators, use external series resistors and gas discharge tubes (gdt). neon lamps are com- monly used as an inexpensive alternative to gdts. these devices can handle the application of large voltages but do not maintain the voltage below the absolute maximum ratings for the AD8233. a complete solution includes further clamping to either supply using additional resistors and low leakage diode clamps, such as bav199 or fjh1100. as a safety measure, place a resistor between the input pin and the electrode that is connected to the subject to ensure that the current flow never exceeds 10 a. calculate the value of this resistor to be equal to the supply voltage across the AD8233 divided by 10 a. radio frequency interference (rfi) radio frequency (rf) rectification is often a problem in applications where there are large rf signals. the problem appears as a dc offset voltage at the output. the AD8233 has a 15 pf gate capacitance and 10 k resistors at each input. this forms a low-pass filter on each input that reduces rectification at high frequency (see figure 60) without the addition of external elements. AD8233 c g c g iaout +in ?in 10k? 10k? 13737-060 figure 60. rfi filter without external capacitors for increased filtering, additional resistors can be added in series with each input. they must be placed as close as possible to the instrumentation amplifier inputs. these can be the same resistors used for overload and patient protection. power supply regulation and bypassing the AD8233 is designed to be powered directly from a single 3 v battery, such as cr2032 type. it can also operate from rechargeable li-ion batteries, but the designer must take into account that the voltage during a charge cycle may exceed the absolute maximum ratings of the AD8233 . to avoid damage to the device, use a power switch or a low power, low dropout regulator, such as the adp150 or adp160. in addition, excessive noise on the supply pins can adversely affect performance. as in all linear circuits, bypass capacitors must be used to decouple the chip power supplies. place a 0.1 f capacitor close to the supply pin. a 1 f capacitor can be used farther away from the device. in most cases, the capacitor can be shared by other integrated circuits. keep in mind that excessive decoupling capacitance increases power dissipation during power cycling. input referred offsets because of its internal architecture, the instrumentation amplifier must be used always with the dc blocking amplifier, shown as hpa in figure 50. as described in the theory of operation section, the dc blocking amplifier attenuates the input referred offsets present at the inputs of the instrumentation amplifier; however, this is true only when the dc blocking amplifier is used as an integrator. in this configuration, the input offsets from the dc blocking amplifier dominate appearing directly at the output of the instrumentation amplifier. if the dc blocking amplifier is used as a follower instead of its intended function as an integrator, the input referred offsets of the in-amp are amplified by a factor of 100. layout recommendations it is important to follow good layout practices to optimize system performance. in low power applications, most resistors are of a high value to minimize additional supply current. the challenge of using high value resistors is that high impedance nodes become even more susceptible to noise pickup and board parasitics, such as capacitance and surface leakages. keep all of the connections between high impedance nodes as short as possible to avoid introducing additional noise and errors from corrupting the signal. to maintain high cmrr over frequency, keep the input traces symmetrical and length matched. place safety and input bias resistors in the same position relative to each input. in addition, the use of a ground plane significantly improves the noise rejection of the system. for wlcsp layout best practices, refer to the an-617 application note .
AD8233 data sheet rev. 0 | page 22 of 29 applications information eliminating electrode offsets the instrumentation amplifier in the AD8233 is designed to apply gain and to filter out near dc signals simultaneously. this capability allows the device to amplify a small ecg signal by a factor of 100 while rejecting electrode offsets as large as 300 mv. to achieve offset rejection, connect an rc network between the output of the instrumentation amplifier, hpsense, and hpdrive, as shown in figure 61. 10k ? iaout hpsense hpdrive s1 gm1 gm2 99r r in+ in? v cm h p a electrode offsets c r = refout b4 c5 a5 a4 b5 c1 13737-061 figure 61. eliminating electrode offsets this rc network forms an integrator that feeds any near dc signals back into the instrumentation amplifier, thus eliminating the offsets without saturating any node and maintaining high signal gain. in addition to blocking offsets present across the inputs of the instrumentation amplifier, this integrator also works as a high- pass filter that minimizes the effect of slow moving signals, such as baseline wander. the cutoff frequency of the filter is given by the following equation: f c = rc ? 2 100 (1) where r is in and c is in farads. note that the filter cutoff is 100 times higher than is typically expected from a single-pole filter. because of the feedback architecture of the instrumentation amplifier, the typical filter cutoff equation is modified by a gain of 100 from the instrumentation amplifier. 50 40 10 20 30 0 0.01 100 10 1 0.1 magnitude (db) frequency (hz) 20db per decade 13737-062 figure 62. frequency response of a single-pole dc blocking circuit as with any high-pass filter with low frequency cutoff, a fast change in dc offset requires a long time to settle. if such a change saturates the instrumentation amplifier output, the s1 switch briefly enables the 10 k resistor path, thus moving the cutoff frequency to f c = )10(2 )10(100 4 4 rc r ? ? (2) for values of r greater than 100 k, the expression in equation 2 can be approximated by f c = c ? 200 1 (3) this higher cutoff frequency reduces the settling time and enables faster recovery of the ecg signal. for more information, see the fast restore circuit section. high-pass filtering the AD8233 can implement higher order high-pass filters. a higher filter order yields better artifact rejection at the cost of increased signal distortion and more passive components on the pcb. two-pole high-pass filter a two-pole architecture can be implemented by adding a simple ac coupling rc at the output of the instrumentation amplifier, as shown in figure 63. 10k ? iaout hpsense hpdrive s1 +in ?in hpa sw 10k ? s2 d4 refout c3 to next stage = refout b4 c5 a5 a4 b5 c1 c2 r1 r2 13737-063 figure 63. schematic for a two-pole high-pass filter note that the right side of c2 connects to the sw terminal. as with s1, s2 reduces the recovery time for this ac coupling network by placing 10 k in parallel with r2. see the fast restore circuit section for additional details on switch timing and trigger conditions. note that, if this passive network is not buffered, it exhibits higher output impedance at the input of a subsequent low-pass filter, such as with sallen-key filter topologies. careful component selection results in reliable performance without a buffer. see the low-pass filtering and gain section for additional information on component selection.
data sheet AD8233 rev. 0 | page 23 of 29 additional high-pass filtering options in addition to the topologies explained in the previous sections, an additional pole may be added to the dc blocking circuit for the rejection of low frequency signals. this configuration is shown in figure 64. 10k ? iaout hpsense hpdrive s1 +in ?in hpa sw 10k ? s2 d4 refout c3 to next stage = refout b4 c5 a5 a4 b5 c1 r1 r2 r comp c2 13737-064 figure 64. schematic for an alternative two-pole, high-pass filter an extra benefit of this circuit topology is that it allows a lower cutoff frequency with lower r and c values. the resistor, r comp , can also be used to control the quality factor (q) of the filter to achieve narrow band-pass filters (for heart rate detection) or maximum pass-band flatness (for cardiac monitoring). with this circuit topology, the filter attenuation reverts to a single-pole roll-off at very low frequencies. because the initial roll-off is 40 db per decade, this reversion to 20 db per decade has little impact on the ability of the filter to reject out of band low frequency signals. the designer may choose different values to achieve the desired filter performance. to simplify the design process, use the following recommendations as a starting point for component value selection. r1 = r2 100 k c1 = c2 r comp = 0.14 r1 the cutoff frequency is located at f c = c2r2c1r1 ???? 2 10 the selection of r comp to be 0.14 times the value of the other two resistors optimizes the filter for a maximally flat pass band. reduce the value of r comp to increase the q and, consequently, the peaking of the filter. note that a very low r comp value may result in an unstable circuit. the selection of values based on these criteria results in a transfer function similar to what is shown in figure 65. when additional low frequency rejection is desired, a high-order, high-pass filter can be implemented by adding an ac coupling network at the output of the instrumentation amplifier, as shown in figure 65. the sw terminal is connected to the ac coupling network to obtain the best settling time response when fast restore engages. 10k ? iaout hpsense hpdrive s1 +in ?in hpa sw 10k ? s2 d4 refout c3 to next stage = refout b4 c5 a5 a4 b5 c1 c3 r1 r2 r comp c2 r3 13737-065 figure 65. schematic for a three-pole, high-pass filter 60 40 20 0 ?20 ?40 ?60 0.01 100 10 1 0.1 magnitude (db) frequency (hz) three-pole filter two-pole filter 40db per decade 40db per decade 20db per decade 60db per decade 13737-066 figure 66. frequency response of the circuits shown in figure 64 and figure 65 careful analysis and adjustment of all of the component values in practice is recommended to optimize the filter characteristics. to reduce the value of r comp , increase the peaking of the active filter to overcome the additional roll-off introduced by the ac coupling network. proper adjustment yields the best pass-band flatness.
AD8233 data sheet rev. 0 | page 24 of 29 table 6. comparison of high-pass filtering options figure to reference filter order component count low frequency rejection capacitor sizes/values signal distortion 1 output impedance 2 figure 61 1 2 good large low low figure 63 2 4 better large medium higher figure 64 2 5 better smaller medium low figure 65 3 7 best smaller highest higher 1 the signal distortion is for the equivalent corner frequency location. 2 output impedance refers to the drive capability of the high-pass filter before the low-pass filter. low output impedance is de sirable to allow flexibility in the selection of values for a low-pass filter, as explained in the low-pass filtering and gain section. the design of the high-pass filter involves trade-offs between signal distortion, component count, low frequency rejection, and component size. for example, a single-pole, high-pass filter results in the least distortion to the signal, but the associated rejection of low frequency artifacts is the lowest of the available filter options. table 6 compares the recommended filtering options. low-pass filtering and gain the AD8233 includes an uncommitted op amp that can be used for extra gain and filtering. for applications that do not require a high order filter, a simple rc low-pass filter is sufficient, and the op amp can buffer or further amplify the signal. refout filtered signal a1 from in-amp stage c r 13737-067 figure 67. schematic for a single-pole, low-pass filter and additional gain a sallen-key filter topology can be implemented for applications that require a steeper roll-off or a sharper cutoff frequency, as shown in figure 68. refout filtered signal a1 from in-amp stage c2 c1 r2 r3 r4 r1 13737-068 figure 68. schematic for a two-pole, low-pass filter the following equations describe the low-pass cutoff frequency (f c ), gain, and q: f c = 1/(2( r1 c1 r2 c2 )) gain = 1 + r3 / r4 q = )1( gainc1r1c2r2c2r1 c2r2c1r1 ?????? ??? note that changing the gain has an effect on q and vice versa. common values for q are 0.5, to avoid peaking, or 0.7 for max- imum flatness and a sharp cutoff frequency. use a high q value in narrow-band applications to increase peaking and the selectivity of the band-pass filter. a common design procedure is to set r1 = r2 = r and c1 = c2 = c, simplifying the expressions for the cutoff frequency and q to f c = 1/(2 rc ) q = gain ? 3 1 note that q can be controlled by setting the gain with r3 and r4; however, this limits the gain to be less than 3. for gain values equal to or greater than 3, the circuit becomes unstable. a simple modification that allows higher gains is to make the value of c2 at least four times larger than c1. note that these design equations only hold true in a case where the output impedance of the previous stage is much lower than the input impedance of the sallen-key filter. the design equations do not hold true when using an ac coupling network between the instrumentation amplifier output and the input of the low- pass filter without a buffer. to connect these two filtering stages properly without a buffer, make the value of r1 at least 10 times larger than the resistor of the ac coupling network (labeled as r2 in figure 63).
data sheet AD8233 rev. 0 | page 25 of 29 driving adcs the ability of AD8233 to drive capacitive loads makes it ideal for driving an adc without an additional buffer. however, depending on the input architecture of the adc, a simple, low- pass rc network may be required to decouple the transients from the switched capacitor input typical of modern adcs. this rc network also acts as an additional filter that can help reduce noise and aliasing. follow the recommended guidelines from the adc data sheet for the selection of proper r and c values. table 7 lists compatible adcs by category. table 7. compatible adcs by category analog-to- digital converters microcontrollers optical sensors accelerometers ad7091 aducm350 adpd103 adxl363 ad7988-1 adpd105 a1 c r adc d1 AD8233 13737-069 figure 69. driving an adc driven electrode a driven lead (or reference electrode) is often used to minimize the effects of common-mode voltages induced by the power line and other interfering sources. the AD8233 extracts the common- mode voltage from the instrumentation amplifier inputs and makes it available through the rld amplifier to drive an opposing signal into the patient. this functionality maintains the voltage between the patient and the AD8233 at a near constant, greatly improving the cmrr. as a safety measure, place a resistor between the rld pin (pin d5) and the electrode connected to the subject to ensure that current flow never exceeds 10 a. calculate the value of this resistor to be equal to the supply voltage across the AD8233 divided by 10 a. the AD8233 implements an integrator formed by an internal 150 k resistor and an external capacitor to drive this electrode. the choice of the integrator capacitor is a trade-off between line rejection capability and stability. it is recommended that the capacitor be small to maintain as much loop gain as possible, around 50 hz and 60 hz, which is typical for line frequencies. for stability, it is recommended that the gain of the integrator be less than unity gain at the frequency of any other poles in the loop, such as those formed by the capacitance and the safety resistors of the patient. the suggested application circuits use a 1 nf capacitor, which results in a loop gain of about 20 at line frequencies, with a crossover frequency of about 1 khz. in a 2-lead configuration, the rld pin (pin d5) amplifier can be shut down or used to drive the bias current resistors on the inputs. although not as effective as a true driven electrode, this configuration can provide some common-mode rejection improvement if the sense electrode impedance is small and well matched.
AD8233 data sheet rev. 0 | page 26 of 29 application circuits heart rate measurement (hrm) next to the heart for wearable exercise devices, the AD8233 is typically placed in a pod near the heart. the two sense electrodes are placed under the pectoral muscles; no driven electrode is used. because the distance from the heart to the AD8233 is small, the heart signal is strong and there is less muscle artifact interference. in this wearable device configuration, space is at a premium. by using as few external components as possible, the circuit in figure 70 is optimized for size. +v s +v s +in ?in hpdrive +v s hpsense iaout refin gnd fr ac/dc rld sdn sdn lod rld rldfb out opamp+ opamp? refout sw AD8233 180k ? 180k ? 10m ? 10m ? 0.1f 10m ? 1nf 10m ? electrode interface 0.1f 0.22f to digital interface signal output 10m ? 13737-070 figure 70. circuit for hrm next to the heart a shorter distance from the AD8233 to the heart makes this application less vulnerable to common-mode interference. however, because rld (pin d5) is not used to drive an electrode, it can be used to improve the common-mode rejection by maintaining the midscale voltage through the 10 m bias resistors. alternatively, tie rld sdn low to save power, and tie the bias resistors to refout. a single-pole, high-pass filter is set at 7 hz, and there is no low-pass filter. no gain is used on the output op amp, thereby reducing the number of resistors for a total system gain of 100. (see figure 71). 70 0 0.1 10k magnitude (db) frequency (hz) 10 20 30 40 50 60 1 10 100 1k 13737-071 figure 71. frequency response for hrm next to the heart circuit the input terminals in this configuration use two 180 k resistors to protect the user from fault conditions. two 10 m resistors provide input bias. use higher values for electrodes with high output impedance, such as cloth electrodes. the schematic also shows two 10 m resistors to set the midscale reference voltage. if there is already a reference voltage available, it can be driven into the refin input to eliminate these two 10 m resistors. exercise applicationheart rate measured at the hands in this application, the heart rate signal is measured at the hands with stainless steel electrodes. the arm and upper body movement of the user create large motion artifacts, and the long lead length makes the system susceptible to common-mode interference. a very narrow band-pass characteristic is required to separate the heart signal from the interferers. rl ra la +v s +v s +in ?in hpdrive +v s hpsense iaout refin gnd fr ac/dc rld sdn lod rld rldfb out opamp+ opamp? refout sw AD8233 22nf 1m ? 1m ? 100k? 3.3nf 100k? 180k ? 180k ? 1m ? 10m ? 10m ? 0.1f 10m ? 1nf 10m ? 10m ? 0.1f 360k ? 0.22f to digital interface signal output 0.22f sdn +v s 13737-072 figure 72. circuit for hrm at hands the circuit in figure 72 uses a two-pole, high-pass filter set at 7 hz. a two-pole, low-pass filter at 24 hz follows the high-pass filters to eliminate any other artifacts and line noise. 70 0 0.1 1k magnitude (db) frequency (hz) 10 20 30 40 50 60 1 10 100 13737-073 figure 73. frequency response for hrm circuit taken at the hands
data sheet AD8233 rev. 0 | page 27 of 29 the overall narrow-band nature of the two-pole, low-pass filter filter combination distorts the ecg waveform significantly. therefore, it is only suitable to determine the heart rate, and not to analyze the ecg signal characteristics. the low-pass filter stage also includes a gain of 11, bringing the total system gain close to 1100. because the ecg signal is measured at the hands, it is weaker than when measured closer to the heart. the rld circuit drives to the third electrode, which can also be located at the hands, to cancel common-mode interference. holter monitor configuration the circuit in figure 75 is designed for monitoring the shape of the ecg waveform. to obtain an ecg waveform with minimal distortion, the AD8233 is configured with a 0.5 hz, single-pole, high-pass filter, followed by a two-pole, 40 hz, low-pass filter. a third electrode is driven for optimum common-mode rejection. 70 0 0.01 1k magnitude (db) frequency (hz) 10 20 30 40 50 60 0.1 1 10 100 13737-075 figure 74. frequency response of holter monitor circuit in addition to 40 hz filtering, the op amp stage is configured for a gain of 2, resulting in a total system gain of 200. keeping the gain lower helps with any motion artifacts picked up in band. to optimize the dynamic range of the system, the gain level is adjustable, depending on the input signal amplitude (which may vary with electrode placement) and adc input range. ra la rl +v s hpsense iaout +v s refin gnd fr ac/dc sdn lod +in ?in hpdrive rld rldfb out opamp+ opamp? refout sw AD8233 5.6nf 499k ? 1m ? 1m ? 5.6nf 150k ? 150k ? 1m ? 10m ? 10m ? 0.1f 10m ? 0.1f 300k ? 3.3f +v s (= +2.5v) electrode interface ...to 11-13 enob adc rld sdn 10m ? +v s 1nf 10m ? +v s 10m ? ...to mcu ...to mcu 0.5hz to 40hz gain = 200 13737-074 figure 75. holter monitor circuit
AD8233 data sheet rev. 0 | page 28 of 29 synchronized ecg and ppg measurement in wearable devices developed for monitoring the health care of patients, it is often necessary to have synchronized measurements of biomedical signals. for example, a synchronous measurement of a ecg and photoplethysmograph (ppg) can be used to determine the pulse wave transit time (pwtt), which can then be used to estimate blood pressure. the circuit shown in figure 77 shows a synchronous ecg and ppg measurement using the AD8233 and the adpd105 photometric front end. the AD8233 implements a two-pole, high-pass filter with a cutoff frequency of 0.3 hz, and a two-pole, low-pass filter with a cutoff frequency of 37 hz. the output of the AD8233 is fed to one of the current inputs of the adpd105 through a 50 k resistor to convert the voltage output of the AD8233 into a current. the ppg signal is acquired by the adpd105 , which is a complete optical transceiver with integrated led drivers, multiple photodiode current inputs, an integrated, 14-bit, successive approximation (sar) adc, and a fifo. in the circuit shown, the chip scale adpd105 is used; the adpd105 is a two input device. the adpd105 is configured to alternately measure the photodiode signal and the ecg signal from the AD8233 on consecutive time slots to provide fully synchronized ppg and ecg measurements. data can be read out of the on-chip fifo or straight from the data registers. the adpd105 channel that processes the ecg signal must be set up in either pulse connect mode or transimpedance amplifier (tia) adc mode, and the input bias voltage must be set to the 0.9 v setting. the tia gain setting can be set to optimize the dynamic range of the signal path. the channel used to process the ppg signal is configured in its normal operating mode. figure 76 shows a plot of a synchronized ecg and ppg measurement using the AD8233 with the adpd105 . 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 time (seconds) shown with f sample = 100hz ppg ecg 13737-078 figure 76. synchronous ecg and ppg measurement using the AD8233 with the adpd105 rl ra la 1.8v 1.8v +in ?in hpdrive +v s hpsense iaout refin gnd fr ac/dc sdn lod rld rldfb out opamp+ opamp? refout sw AD8233 6.8nf 1m ? 1m ? 250k ? 2.7nf 100k ? 180k ? 180k ? 1m ? 10m ? 10m ? 0.1f 10m ? 1nf 10m ? 10m ? 0.1f 360k? 4.7f to digital interface 4.7f rld sdn 1.8v 50k ? pd3-4 pd1-2 pdc ledx1 vled vref 1f agnd dgnd lgnd 0.1f 0.1f dvdd avdd 1.8v 10k ? 10k? 1.8v scl sda gpio0 gpio1 to digital interface adpd105 13737-077 figure 77. synchronous ecg and ppg measurement circuit
data sheet AD8233 rev. 0 | page 29 of 29 packaging and ordering information outline dimensions a b c d 2.080 2.040 2.000 1.745 1.705 1.665 12 345 bottom view (ball side up) top view (ball side down) ball a1 identifier 0.560 0.500 0.440 0.330 0.300 0.270 side view 0.230 0.200 0.170 0.300 0.260 0.220 coplanarity 0.04 seating plane 12-10-2015-a pkg-003315 1.20 ref 1.60 ref 0.40 bsc 0.252 ref 0.18 ref 0.26 ref figure 78. 20-ball, backside-coated, wafer level chip scale package [wlcsp] (cb-20-13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD8233acbz-r7 ?40c to +85c 20-ball, backside-coated , wafer level chip scale package [wlcsp] cp-20-13 AD8233cb-ebz evaluation board 1 z = rohs compliant part. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13737-0-8/16(0)

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